The present invention generally relates to semiconductor manufacturing, and more particularly to fin field effect transistor devices (FinFET) having a source drain with proper overlap.
Complementary Metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FET) as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. Most common among these may be metal-oxide-semiconductor field effect transistors (MOSFET), in which a gate structure may be energized to create an electric field in an underlying channel region of a substrate, by which charge carriers are allowed to travel through the channel region between a source region and a drain region of the substrate. The portion of a fin not covered by the gate structure may define a source drain region of the semiconductor device. The length of the channel region directly affects the functionality of the FET. As ICs continue to scale downward in size, an overlap may be needed between the gate and the source drain region.